Hardware tracing/logging for highly integrated embedded controller device

ABSTRACT

A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.

FIELD OF THE INVENTION

This invention relates to processor controlled circuitry and, inparticular, to processor controller circuitry embedded on a chip inwhich the internal busses of the circuitry are not directly accessible.

PROBLEM

Embedded processor controller circuitry is used in various applications.One such application is an interface controller for use with computerperipheral storage devices, such as disk drives, CD-ROMs, and tapedrives. A processor and a memory of the interface controller controldata transfer operations between a host and the peripheral data device.In disk drive applications, the interface comprises a disk drivecontroller that controls data transfer operations between a disk driveand a host.

In the testing of a prototype disk controller during its development, itis necessary to trace the program flow and monitor data content onvarious busses during hardware and firmware development. This can bedone by using an in circuit emulator. The in circuit emulator isconnected to the target device (the device under test) through theprocessor address, data, and control buses of the target device. The incircuit emulator acts like the processor of the target device during thedevelopment and testing. The in circuit emulator provides programexecution and data/program tracing function.

It is difficult to provide satisfactory hardware connections between thetarget device and the in circuit emulator. There are significant numberof signals required to be connected from the in circuit emulator to thetarget device. These connections often requires expensive connectorsbecause the processor on the target device usually has a special packagefootprint. Even with adequate connections to these elements, there arealso noise problems on the signal lines.

Real time debugging is also difficult with the in circuit emulatorbecause the emulator often can not match the emulated processoroperation speed. As a result, the target program is executed at theemulator clock rate instead of the target circuit's clock rate.

A second method to develop the target device hardware and firmware is totrace the program flow and data content by an analyzer, such as a ROMemulator. Similar to the in circuit emulator, the ROM emulator connectsto the processor address/data/control lines on the target device. Thedifference between the in circuit emulator and the ROM emulator is thatthe ROM emulator does not replace the processor function on the targetdevice. The processor on the target device still acts as the centralcontrol unit to direct the program and data flow. The ROM emulator'sfunction is to trace the address and data buses signals while the targetprocessor is in execution. A control program in the ROM emulatortranslates bits/bytes information into the original source code of thetested circuit so engineers can debug the code. This reduces costsignificantly from the first method because the ROM emulator does notprovide the processor function. This ROM emulator method also providesan improved product real time debugging capability.

Multiple chips were formerly used in a target product and were combinedinto single chip as the technology advanced. The traditional stand aloneprocessor was also combined into the single chip along with otherelectronics parts on the target device. The external program and databusses then become internal to the chip. Because of the cost andpackaging limitation on the input/output pin count on a single chipdevice, the program and data buses and some control signals are nolonger available for program or data tracing. As the result, developmenttesting on the product become extremely difficult.

As a temporary solution, specific events or data are stored into abuffer memory by the firmware control on the target device. Thisinformation then can be retrieved and analyzed to understand the deviceoperation. However, there is a major drawback on this approach. Itrequires additional firmware and processor time to fetch and process thetraced data. All data tracing and logging processes with the data bufferis controlled by the microprocessor in real time. This additionalprocesses reduce the amount of time the processor has to perform it'snormal operations. As the result, it changes the code execution timingso that a problem that exists in a real time mode may not be re-producedin the debug mode timing.

SOLUTION

The above and other problems are solved and an advance in the art isachieved by the present invention which is directed to internal tracingcontrol circuitry embedded on the same chip containing the targetdevice. The embedded tracing hardware on the process controller chip iscontrolled by the embedded firmware. Upon powering up the target device,the embedded firmware initializes the tracing control logic to a presetcondition. The tracing feature can initially be disabled as the presetcondition. With the embedded firmware, the tracing feature can beenabled through a serial port or a standard industrial interface such asan ATA (AT Attachment) interface or other technique. The enablingfunction can be done by sending the request through the interface by acomputer terminal.

The traced information is written into a buffer memory through anembedded buffer memory manager. The buffer memory manager supportsmultiple data ports access on the target device. In addition to a tracedata port created by the invention, there are disk, host, servo, ECC,and microprocessor ports existing on a normal computer storage devicesuch as a disk drive. The buffer memory manager also provides prioritycontrol for these data ports, so that time critical data will betransferred in and out of the buffer memory first. Non-time criticaldata, such as data accessed by the microprocessor and host port will bescheduled after the time critical data is processed. Each data port alsoprovides data FIFO (first in first out buffering device) to prevent anydata loss due to port's lower priority accessibility. With thisautomatic control mechanism, the traced data can be logged into thebuffer memory in real time without the microprocessor intervention. Asthe result, the trace function of the invention will not interfere theregular device operations.

The tracing buffer memory of the present invention is a section of databuffer memory normally used for the target product's normal operations.For a disk drive device, the normal operations are reading and writingdata in and out the disk. A dedicated section of the data buffer memoryis allocated for the tracing function during the debugging developmentstage. The allocation can be implemented by set a BOS (beginning ofmemory segment), EOS (end of memory segment), LPR (last view pointer),and TPR (trace pointer) pointers. The trace pointer points to the nextfree buffer memory location for the next tracing data operation. Thetrace pointer loads the BOS content if it passes the EOS. The lastdisplay pointer points to the last viewed traced content. A flexiblesize of circular tracing data buffer memory is created with thesepointers supports. This circular buffer then can be used to trace allthe internal interface controller activities.

To view the traced data stored in buffer memory, the same computerterminal used to enable the tracing control logic operation can be usedagain. With the embedded firmware control, the target device processorreceives the tracing request from the terminal. The processor thenfetches the traced data from the buffer memory through themicroprocessor port. The trace data is transmitted to the terminal viathe serial port or an industrial standard interface. Depending on thetarget device firmware implementation, raw traced data stored in thedata buffer can be processed internally in the target device orprocessed after the data is transmitted to the computer terminal. It ispreferable to decipher the raw traced data content with the computerterminal program because of the target device program space constraints.

Viewing the data in the trace buffer memory is normally not a timecritical task compared with the read and write function on a targetdevice such as a disk drive device. Because the traced data is forhardware and firmware debugging purposes, the traced data can beprocessed in a non-real time mode. The embedded processor can be used tofetch the data from the buffer memory and transfer the data to theterminal. However, if the real time mode is desired, the traced data canbe fetched through a data port and then can be automatically transferredto the computer terminal without target processor intervention. One suchdata port that can be used for this transfer is the host data port. Ifthere are no host transfer activities, the host port can be used totransfer traced data to a computer terminal with a standard industrialinterface. If the host port is not available, an additional data portcan be created for this purpose. The traced data then can be transferredto a terminal through a serial port interface without target processorintervention.

Normally a target device such as a disk drive provides a memory databuffer of sufficient size for host and disk data transfer. Since thememory is already available, the allocation of a small section of thismemory will not affect the normal device operation. It is more desirableto use this memory data buffer for storing the traced data compared to adedicated tracing memory. If the target device does not have sufficientsize of data buffer for tracing (such device may have a small size databuffer memory during regular use), a larger data buffer memory may beused only during the hardware and firmware debugging development stage.Once the debugging process is completed, the target device can bedelivered to user with normal size buffer memory.

The present invention can be applied to all single chip embeddedprocessor controlled circuitry applications. It is not limited toprocessor controlled peripheral data storage controller devices. It canbe used for all embedded circuitry having debugging limitations.

DESCRIPTION OF THE DRAWINGS

These and other advantages and features of the invention maybe betterunderstood from a reading of the following detailed description taken inconjunction with the drawings in which:

FIG. 1 discloses a system embodying the invention.

FIG. 2 discloses further details of disk controller 103 of FIG. 1.

FIG. 3 discloses further details of buffer memory controller 202 of FIG.2.

FIG. 4 discloses further details of the buffer memory multiplexor 301 ofFIG. 3.

FIG. 5 discloses further details of ROM 112.

FIG. 6 discloses further details of buffer memory 104.

FIG. 7 discloses further details of tracing control logic 302.

DETAILED DESCRIPTION

Description of FIG. 1

FIG. 1 discloses a computer controlled system 100 comprising host 101,disk controller 103 and disk drive assembly 107. The system of FIG. 1further includes buffer memory 104, ROM 112 and terminal 110. Host 101is connected by path 102 to disk controller 103. Disk controller 103 isconnected by path 106 to disk drive assembly 107. Host 101 may comprisea computer, such as a personal computer, that communicates via diskcontroller 103 with a bulk data storage device such as disk driveassembly 107. Host 101 sends write commands and data via disk controller103 to disk drive assembly 107 to write data onto the medium comprisingthe disk drive assembly. Host 101 may also send read commands via diskcontroller 103 to disk drive assembly 107 to retrieve priorly writtendata the host requires. On both read and write operations, the datatransmitted from the host via the disk controller to the disk driveassembly includes an identity of the location on the disk drive assemblythat contains the data that is to be retrieved on a read operation or tobe written on a write operation. This data may comprise anidentification of the cylinder, track and sector to which the newinformation is to be written or from which priorly written informationis to be retrieved.

The data that is exchanged between host 101 and disk drive assembly 107does not pass instantaneously through disk controller 103. Instead, thedata to be exchanged is received by disk controller 103, temporarilystored in buffer memory 104 and then subsequently transmitted to thedestination circuit, i.e. disk drive assembly 107 or host 101. Buffermemory 104 is used for this purpose because of the different speeds atwhich host 101 and disk drive assembly 107 operate. Host 101 operatesand applies data to path 102 at a first data rate while disk driveassembly 107 operates at a different data rate.

Terminal 110 is provided in accordance with the present invention toprovide a user with direct access to the internal circuitry, such asmicroprocessor 111, within disk controller 103. These connections areshown in greater detail on the subsequent drawing Figures. The purposeof terminal 110 is to facilitate testing and diagnostic operations ofthe disk controller during design and development of the diskcontroller. ROM 112 functions as subsequently described and permanentlystores the programs needed by microprocessor 111 to control theoperation of the disk controller.

Description of FIG. 2

Disk controller 103 is shown in further detail on FIG. 2 as comprisingbuffer memory controller 202, host interface controller 201, programmemory controller 211, serial port 204, microprocessor 111, diskinterface/ECC controller 203, servo controller 207, and a bus system 209which interconnects these circuits for the exchange of signals necessaryin the operation of disk controller 103. The bus system 209 includes acontrol bus, an address bus, and a data bus.

The operation of disk controller 103 is controlled by microprocessor 111which exchanges signals over bus system 209 with the various circuitscomprising disk controller 103.

In operation, disk controller 103 on FIG. 2 receives read and writerequests from host 101 via the bus 102 and host interface controller201. Each received request is transmitted over bus system 209 tomicroprocessor 111. In serving these requests, microprocessor 111communicates with host interface controller 201 and buffer memorycontroller 202 via the bus system 209 to cause the data received by hostinterface controller 201 to be extended via data bus 212 and control bus213 to buffer memory controller 202. Buffer memory controller 202 thensends the required signals over the address and control bus of bussystem 105 to cause buffer memory 104 to write the data on the data busof bus system 105 into buffer memory 104. This data is temporarilystored in buffer memory 104 and then subsequently transmitted to diskdrive assembly 107.

The following describes how the data temporarily stored in buffer memory104 is transmitted to disk drive assembly 107. The first step in thisoperation is that buffer memory controller 202 reads the host data outof buffer memory 104 and transmits the necessary data and controlsignals over busses 214 and 216 to disk interface/ECC controller 203.This circuit extends the data over the data bus of bus system 106 todisk drive assembly 107. Disk drive assembly 107 also receives controlsignals over the control busses of bus system 106. Disk drive assembly107 performs the operations required to write the data received onto theappropriate portion of the disk drive assembly. The information receivedby disk drive assembly 107 to perform this operation includes servoinformation from servo controller 207. This circuit provides thefunction of providing spindle position, VCM, demodulator timingcontroller, gray code and position analog data acquisition as requiredby the disk drive assembly to perform the function requested by thehost.

The preceding has described the receipt by disk controller 103 of arequest from the host and how this request is served by disk controller103. If the host request is a write operation, the data specified by thehost is written into disk drive assembly 107 as above described. If thehost request is for a read operation, the request is served in much thesame manner except that the signals received by disk interface/ECCcontroller 203 and servo controller 207 cause the data requested by thehost to be read by disk drive assembly 107 and transmitted via diskinterface/ECC controller 203 to buffer memory controller 202. Thisinformation is then temporarily written into buffer memory 104 followingwhich it is read out of the buffer memory and transmitted through hostinterface controller 201 and over path 102 to host 101.

Microprocessor 111 performs the operations required of it in response tothe reception of a host request as above described. In so doing,microprocessor 111 operates under control of programs stored in ROM 112.

Description of FIG. 3

FIG. 3 discloses further details of disk controller 103. Disk controller103 is shown as comprising buffer memory controller 202, microprocessor111, serial port 204, host interface controller 201 which comprises hostinterface control logic 310 and its associated host fifo 308, diskinterface/ECC controller 203 and its fifo's 309, 311, and 312 and diskinterface/ECC control logic 321. The system of FIG. 3 further includesbuffer memory 104 connected by bus system 105 to buffer memorycontroller 202.

Buffer memory controller 202 includes buffer memory multiplexor 301,tracing control logic 302 and its associated fifo 305 and DRAM refreshcontrol logic 303. Buffer memory multiplexor 301 is connected to buffermemory 104 by bus system 105. It is further connected to host interfacecontrol logic 310 by host fifo 308 and bus 212. It is further connectedto fifo's 309, 311 and 312 by paths 214. It is further connected to ROM112 and microprocessor 111 and terminal 110 by bus system 209.

It has already been described how the serving of a host write requestinvolves the transmission of data from host 101 to disk drive assembly107 via host interface controller 201, buffer memory controller 202,disk interface/ECC controller 203 and over path 106 extending to diskdrive assembly 107. It has also been described how the serving of a hostread request involves the transmission of signals from the host to thedisk drive assembly specifying the memory location to be read as well asthe transfer from the disk drive assembly back to the host of the dataread from the disk drive assembly in response to the reception of thehost read request. It has further been described how the information anddata that is exchanged between the host and the disk drive assembly onread/write requests is not transmitted directly through buffer memorycontroller 202, but instead, it is transferred from buffer memorycontroller 202 to buffer memory 104 on a write operation and is thensubsequently read out of buffer memory 104 and transferred to either thehost or the disk drive assembly depending upon the direction of dataflow. The following describes in greater detail the function of buffermemory 104 in the serving of host read and write requests.

The serving of host read and write requests involves the use of buffermemory 104 not only to exchange data between host 101 and disk driveassembly 107, but to apply information at selected times to the variouscircuits shown on FIG. 3. The serving of each host request involves thesequential connection of buffer memory 104 to the various circuits shownon FIG. 3. Buffer memory multiplexor 301 comprises a multi-portmultiplexor which, on its lower side, is connected to the variouscircuits of FIG. 3 that require a connection to buffer memory 104. Thetop side of buffer memory multiplexor 301 is connected over bus system105 to buffer memory 104. In the serving of host requests, buffer memorymultiplexor 301 is controlled by circuits in 301 and the other circuitsshown on FIG. 3 to establish a plurality of connections, one at a time,from the various inputs of multiplexor 301 to the output of multiplexor301 and, in turn, to buffer memory 104.

Path 212 connects host interface controller 201 to an input of buffermultiplexor 301. Buffer memory multiplexor 301 detects the reception ofa request by host interface controller 201 and causes input 212 ofmultiplexor 301 to be connected to the output of multiplexor 301 andover bus system 105 to buffer memory 104.

If the host request represents a read request, buffer memory multiplexor301 causes the data read out of disk drive assembly 107 to be writteninto buffer memory 104. Path 214 is then disconnected from the input ofmultiplexor 301 and path 212 is connected through the multiplexor and tobuffer memory 104. Path 212 receives the data read from the buffermemory 104 and extends this data through fifo 308 and host interfacecontrol logic 310 to host 101.

If the host request represents a write request, buffer memorymultiplexor 301 causes the data received from the host to be writteninto buffer memory 104. Path 212 is then disconnected from themultiplexor 301 and path 214 is connected through the multiplexor tobuffer memory 104 over bus system 105. Path 214 receives the data readfrom the buffer memory 104 and extends this data through fifo 311 andthen through disk interface/ECC control logic 321 to disk drive assembly107.

To support both write or read requests from the host to the disk driveassembly 107, specific servo data is stored in buffer memory 104 tospecify the disk drive assembly media track format. The servo data istransferred to disk interface/ECC control logic 321 through servo dataFIFO 309 and path 313. For the host write operation, when themultiplexer disconnects path 212 after transferring a portion of hostdata to buffer memory and is ready to transfer the data to disk driveassembly 107, servo data path 313 is connected first before the diskdata path 314 is transmitted. The servo data is transferred through overpath 313 and FIFO 309 to disk interface/ECC control logic 321. Path 313is disconnected and data path 314 is connected to the buffer memory.Using this servo data, the disk data is written in the correct locationon the disk drive assembly. When the host request is a read request,servo data path 313 is first connected to buffer memory 104. The servodata is used to locate the disk data on the disk drive assembly. Then,the disk data path 314 is connected to transfer the data from disk driveassembly 107 to buffer memory 104.

If this host request represents a read request and there is read errordetected by the disk interface/ECC control logic 321, ECC data path 315and FIFO 312 are connected to the buffer memory 104 at a time when thereis no connection from buffer memory 104 to the servo data path 313 anddisk data path 314. The ECC correction is done by using the ECC datapath 315 to buffer memory 104. The ECC control logic fetches the datafrom buffer memory and performs necessary correction procedures. The ECCcontrol logic then writes the data back to buffer memory 104 through thepath 315.

If buffer memory 104 is a DRAM device, memory refreshing is required toprevent data loss. Path 307 extending from DRAM refresh control logic303 is periodically enabled and extended through multiplexor 301 tobuffer memory 104 over the address bus 105 to provide the requiredrefresh signals to buffer memory 104.

Microprocessor 111 also can be connected through multiplexer 301 toaccess buffer memory 104. Data in buffer memory 104 can be read orwritten by microprocessor over bus 209. This path is connected to themultiplexer if there are no other connection at the time. It has thelowest priority.

The present invention solves the data tracing and logging problem byproviding tracing control logic 302 in buffer memory controller 202. ROM112 provides the firmware to support the data tracing and loggingfunction. The tracing function is enabled when tracing control logic 302and microprocessor 111 receive a request from a developer throughterminal 110. Specific program address or data can be passed to tracingcontrol logic 302 from terminal 110. Then the tracing control logic 302can monitor the data or address busses for the presence of thesespecific program addresses or data once it is enabled. When the programin ROM 112 is stepped through the specified program addresses to betested and, in response to the advancement of each step through theprogram, tracing control logic 302 extends the signals on the addressand data busses to a trace data segment of buffer memory 104 where theyare recorded and written for further use by the developers. In so doing,tracing control logic 302 reads the specified data and address bussignals 209, extends them through tracing data fifo 305 and over paths304 which is an input to multiplexor 301. This input is activated whenrequired to extend the tracing data through the multiplexor and overpath 105 for recording in a specified segment of buffer memory 104.

Terminal 110 is connected via bus 109 and serial port 204 to the dataaddress and control busses of bus system 209. Terminal 110 is providedprimarily for testing purposes and its connections to bus system 209enable the designers and testing personnel to communicate withmicroprocessor 111 and the other elements of disk controller 103 inorder to facilitate the testing required during the development andtesting phases of disk controller 103.

Description of FIG. 4

FIG. 4 describes further details of buffer memory multiplexor 301 ofFIG. 3 as well as disk controller 103. FIG. 4 shows host interfacecontrol logic 310 and its associated fifo 308 which receives requestsfrom host 101 over path 102. The system of FIG. 4 further includesmicroprocessor 111, terminal 110 and its associated serial port 204 andROM 112. FIG. 4 further includes disk interface/ECC control logic 321which is connected over path 106 to disk drive assembly 107. FIG. 4further includes buffer memory 104 which is connected by bus system 105to gates 401-406.

Buffer memory multiplexor 301 on FIG. 3 comprises the elements shownwithin rectangle 301 on FIG. 4. These elements include buffer accesscontrol 450 and gates 401-406. Gates 401-406 comprise a six inputmultiplexor and each gate may be activated one at a time to connect itsinput through the multiplexor to buffer memory 104 via data bus 105D.Each gate 401-406 has a data input and a control lead which, whenactivated, connects its data input over data bus 105D to buffer memory104. "BI-directional" gate 401 serves host interface control logic 310and its associated fifo 308 and when activated by a signal on path 411,connects path 212 through gate 401 and over data bus 105D to buffermemory 104. Gate 402 serves tracing data fifo 305 and when gate 402 isactivated by a signal on path 412, extends data on path 304 through gate402 and over data bus 105D to buffer memory 104. Gate 403 servesmicroprocessor data fifo 433 and when gate 403 is activated by a signalon path 413, it connects microprocessor data fifo 433 over path 443through gate 403 to buffer memory 104.

Gate 404 is activated by a signal on path 414 and at such times, itconnects disk interface/ECC control logic 321 via fifo 311 to buffermemory 104. At such times, information can be exchanged on a read orwrite operation between buffer memory 104 and disk drive assembly 107.Gate 405 is activated by a signal on path 415 at such time connects fifo309 with disk interface/ECC control logic 321 to transmit servo datafrom buffer memory 104 to disk interface/ECC control logic 321. Gate 406is activated by a signal on path 416 to connect ECC fifo 312 with buffermemory 104. This connection enables buffer memory 104 to exchange ECCinformation with disk interface/ECC control logic 321.

A multiple level of enabling control is used depending on the productoperation mode, such as normal function mode, self monitoring mode, orprogram debugging mode. Embedded hardware monitors the internal programand data address bus lines of the processor. A defined range of programaddresses or data content can be programmed into tracing control logic302. A defined range of data content on data bus 209D is useful fordebugging since this enables the data addresses and content to be loggedinto buffer memory 104 when embedded microprocessor 111 reads or writesthis address range. If a certain program address is critical fortroubleshooting, the logging function is triggered when the embeddedprocessor 111 fetches the instruction from this address.

The data structure for the traced data can be specified by a certainprefix for program addresses and another prefix for data addresses.Additional information, such as microprocessor read or write operationcan also be logged. The next trace entry in the data structure can bebased on program instruction or data content. Depending on theapplication, various types of data structure can be used.

Description of FIG. 5

FIG. 5 discloses further details of ROM 112. ROM 112 is subdivided intotwo segments. The first segment is entitled normal read/write programsand numbered 501. The second segment is entitled tracing functionprogram 502. ROM operates under control of signals on address bus 209A,control bus 209C, and data bus 209D.

ROM segment 501 is used during the normal read/write functions of thedisk controller in which data is exchanged between host 101 and diskdrive assembly 107. ROM segment 502 is used in connection withmicroprocessor 111 to control the operation of the system in tracinginformation on address bus 209A and data bus 209D and controllablyentering it into buffer memory 104 via tracing control logic 302,tracing data fifo 305 and gate 402.

Description of FIG. 6

FIG. 6 discloses further details of buffer memory 104 which as shown onFIG. 6, is divided into a read/write function 601, a tracing controlfunction 602, and an additional read/write function 603. The read/writefunction segments 601 and 603 store the information and data required inthe exchange of data between the host 101 and disk drive assembly 107via the disk controller 103 of the present invention. Tracing functionsegment 602 stores address and data written into buffer memory 104 undercontrol of the tracing circuitry of the present invention.

The beginning address of the tracing function segment 602 is identifiedon FIG. 6 as BOS while the ending address of segment 602 is identifiedas EOS. Tracing function segment 602 is associated with softwarepointers 604 and 605. Pointer 604 is termed the trace pointer; pointer605 is termed the last view pointer.

Both pointers 604 and 605 are movable. Both pointers are initialized tothe BOS address. When a tracing function is performed, information iswritten into segment 602 location by location and the trace pointer 604moves from position to position. When the trace pointer 604 reaches theend of segment address EOS, it wraps around the segment and goes back tothe BOS address and then continues advancing from there.

Last view pointer 605 does not advance in unison but with the tracepointer 604. However, at the end of a tracing operation when the userwishes to view or retrieve the information that was stored in segment602, last view pointer 605 advances location by location and remains atthe location in segment 602 that represents the last information thatwas retrieved by an operator at terminal 110.

After tracing pointer 604 enters information into a portion of memorysegment 602, say the first half, the user, can read this information outwhen the logging or tracing is finished. The last view pointer is thenactive and when the last view pointer reaches the location of the tracepointer 604, this indicates that all of the information that was tracedand stored had been retrieved and that no additional information isavailable.

Let it be assumed that pointers 604 and 605 are initially at the samelocation of segment 602. Assume that a new trace starts and tracepointer 604 advances as information is entered into segment 602. Whenthe trace pointer 604 reaches the EOS address, it wraps back to the BOSaddress and the writing of new information continues up to the pointwhere the address of trace pointer 604 matches that of last view pointer605. At this time, the trace command originally generated by user atterminal 110 may let the trace pointer 604 continue logging andoverwrite the information it just wrote. As an alternative, the commandgenerated by the user may not permit overwrite and in that case, whenthe call trace pointer reaches the location of the last view pointer,call tracing and logging stops and information is not overwritten. Ifinformation overwrite is permitted, the tracing and logging operationwill continue and new data will be entered into segment 602 until theuser terminal 110 issues a command to stop the operation.

Trace pointer 604 and last view pointer 605 are software pointersgenerated by the microprocessor 110 and written into tracing controllogic 302 to tell the tracing function to stop at a specified address,namely to tell the tracing control logic that when the tracing pointer605 equals the last view pointer 604 that tracing control logic shouldnot send to any further addresses via the tracing data fifo 305 tobuffer memory 104.

Description of FIG. 7

FIG. 7 discloses further details of tracing control logic 302. Thiselement comprises address tracing logic 701, data tracing logic 702,logic control 703, address logic 708, and multiplexor 707. Address logicreceives the addresses of address bus 209A and data bus 290D that are tobe traced and information therefore entered into buffer memory 104.Logic control 703 and address logic 708 receive control signals fromcontrol bus 209C and CTRL path 306 to control the operation of tracingcontrol logic circuit 302 in performing its address and data tracing andlogging functions. One such function performed by logic control 703 isto apply the necessary signals to multiplexor 707 so that either path704 from address tracing logic 701 or path 705 from data tracing logicelement 702 is extended through multiplexor 707 to output path 302extending through the circuitry shown on FIGS. 3 and 4 to buffer memory104. Control logic 302 also receives address signals from bus 209A anddata from bus 209D.

The following describes how disk controller 103 performs tracing andlogging functions.

    ______________________________________                                        1.  It can trace and log all and program addresses currently being                executed by microprocessor 111.                                           2.  It can trace and log specified addresses on address bus 209A.             3.  It can trace and log specific data on data bus 209A.                      4.  It can log a range of addresses on address bus 209A.                      5.  It can log a range of data on the data bus 209D.                          6.  It can perform selected combinations and multiples of the above 5             described functions.                                                      ______________________________________                                    

Let it be assumed that a user at terminal 110 desires to trace anoccurrence of ROM 112 address 103 on address bus 209A. This being thecase, the user at terminal 110 sends a trace command to microprocessor111 over bus system 209 specifying that ROM 112 address 103 is to betraced. Microprocessor 111 receives the trace command and sends commandsover bus system 209 to ROM 112 to access the tracing program portion 502of ROM 112 as shown in FIG. 5. Microprocessor 111 executes the tracingprogram and causes signals to be sent over bus 209 to tracing controllogic 302 which is shown in further detail on FIG. 7. The addresssignals on bus 209A are applied to address tracing logic 701 as well aslogic control 703 and in particular, to address logic element 708 withinlogic control 703. Address logic 708 stores the address 103 that is tobe traced.

Microprocessor 111 then resumes its normal functions of controlling thecircuitry on FIG. 4 for the serving of host read and write commands inwhich data is exchanged between host 101 and disk drive assembly 107 asdescribed. In serving the normal functions of disk controller 103,microprocessor 111 executes the normal read/write programs in segment501 of ROM 112 as shown on FIG. 5. Operations continue with normalread/write functions being served until such time as microprocessor 111addresses a program in ROM segment 501 having an address of 103. This isthe address that the system is now conditioned to trace. At this time,address logic 708 and the remainder of logic control 703 detects theappearance of ROM address 103 on bus 209A. In response to thisdetection, logic control 703 applies a signal to path 706 tointerconnect multiplexor input 704 with multiplexor output 320. At thesame time, logic control sends a signal over path 710 to activate gatesin address tracing logic 701. The activation of these gates causes themto extend address 103 on bus 209A through address tracing logic 701,over path 704, multiplexor 707, path 320 to tracing data fifo 305. Fromthere, it is extended over path 304, and through gate 402 and data path105D to buffer memory 104 where it is written into the tracing functionsegment 602 of buffer memory 104 as shown on FIG. 6.

If the buffer memory segment 602 on FIG. 6 is initially empty, tracepointer 604 is at segment address BOS. When ROM program address 103 isexecuted, information is written for address 103 into buffer memorysegment 602 beginning at the BOS. Next program address 104 is executedand written into segment 602. This continues until EOS is reached. Thetracing pointer then wraps around back to BOS. There are two modes oftracing. The first is continuous tracing operation which continuestracing until the user stops it. The second mode is that tracing isstopped when the trace pointer 604 location indicates the address oflast view pointer 605.

The trace and last view software pointers 604 and 605 are controlled byaddress control logic 451 which applies the necessary addresses to path105A shown on FIG. 4 extending to buffer memory 104 to cause the ROMaddress 103 to be written into an address of tracing function segment602 of buffer memory 104 on FIG. 6. Once the specified ROM address 103is detected on address bus 209A, tracing control logic 302 and it'saddress logic 708, respond to this detection by sending a signal overCRTL path 306 to address control logic 451 on FIG. 4. Under normaloperations, in which tracing functions are not being executed, addresscontrol logic receives address generated by microprocessor 111 andapplied to address bus 209A. It extends these signals over address bus105A to buffer memory 104A to control the writing of data associatedwith host read and write requests into buffer memory 104 and inparticular, into read and write functions 601 and 603 of buffer memory104. However, when a specified ROM address 103 that is to be traced isdetected by address logic 308, address control logic 451 is notified ofthis detection by the signal on path 306 from tracing control logic 302and asserts control of the addressing of buffer memory 104 and causesthe detected ROM address 103 to be written into the appropriate addressof tracing function segment 602 of buffer memory 604. Following thewriting of ROM address 103 into buffer memory 104, the system reverts toits normal operation and serves host read and write requests. At thistime, control of the addressing of buffer memory 104 is returned tomicroprocessor 111 and the addresses received by address control logic451 are extended by it from address bus 209A to address bus 105Aextending to buffer memory 104.

If a continuation of logging is desired, logging will not stop and thetrace pointer moves until stopped by the user. Continuous logging isstopped when terminal 110 and serial port 204 send a stop command tomicroprocessor 111 which communicates with ROM 112 to execute a stopprogram for tracing. This sends the necessary signals up over bus system209 to tracing control logic 302 to terminate the tracing operation.When tracing is stopped, the trace information is still in buffer memory104.

The traced addresses stored in tracing function segment 602 of buffermemory 104 may be retrieved under control of a user at terminal 110 whogenerates a read out command which is extended through serial port 204over the bus system 209 to microprocessor 111. Microprocessor addressesthe tracing function segment 502 of ROM 112 to execute the read outcommand. In so doing, signals are sent to address control logic 451 tocause it to read out the tracing function segment 602 of buffer memory104. The data that is read out is applied by buffer memory 104 to databus 105D and extended through gate 403 which is activated at this timeover path 413 by buffer access control 450. The read out data extendedthrough gate 403, is applied over path 443 to microprocessor data fifo433 and from there over path 444 to microprocessor 111. Themicroprocessor then extends the data over data bus 209D, and serial port204 to terminal 110.

A user at host 101 may also initiate a trace operation and a subsequentdata read out operation in a manner similar to that just described forterminal 110. In this case, the host initiated trace command is receivedby host interface control logic 310 and extended to microprocessor 111over bus 209. The trace command is received by microprocessor 111 andexecuted by it in the manner described for a trace command initiated byterminal 110. Subsequently, a user at host 101 may retrieve the traceinformation from segment of 602 of buffer memory 104. The read out ofbuffer memory of 104, at this time, causes the traced data to be appliedto data bus 105D, extended through gate 401 which is activated at thistime by path 411 and buffer access control and applied to over path 212to host fifo 308. From there, the read out trace data is extended overpath 317 and host interface control logic 310 and back to host 101 overpath 102.

The preceding has described the tracing of a single ROM address 103. Thetracing facilities of the present system permit other types of tracingas above described. Namely, continuous tracing, the tracing of asequence comprising a plurality of ROM addresses, or the tracing ofspecified data on data bus 209D rather than specified addresses onaddress bus 209A. Logic control element 703, and its address logic 708contains the necessary registers comparators and logic to permitcontinuous tracing to be done, to permit a range of addresses to betraced as well as the tracing of a single specified address such as 103as already described.

If the system has sufficient band width capabilities it can handletracing and logging functions as well as normal functions. On the otherhand, if sufficient spare band width does not exist, then it can't do,simultaneously, both normal functions and tracing functions. In thatcase, the only program information that is logged and traced areprograms that involve branch conditions. This branch conditioninformation is useful by the terminal and its operator to analyze systemconditions.

When specific data on data bus 209D is to be traced, signals to thiseffect are sent over bus system 209 to logic control 703 which, in turn,sends an activation signal over path 709 to data tracing logic 702 toprepare it for the detection of the specified data on bus path 209D.Logic control 703 causes a signal to be sent over path 706 tomultiplexor 707 to cause it to interconnect its input 705 from datatracing logic 702 with its output on path 320. The specified data isdetected and extended through data tracing logic 702, over path 705 andthrough multiplexor 707 to path 320 and the remainder paths previouslydescribed to cause it to be written into the appropriate address andtracing function segments 602 of buffer memory 104.

The disk controller comprising the subject matter of this invention isan improvement of a disk controller manufactured by Adaptec, Inc. of 691South Milpitas Boulevard, Milpitas, Calif. 95035. This Adaptec, Inc.disk controller is disclosed in a manual dated Sep. 10, 1997 andentitled AIC-5460A Drive Manager chip. The contents of this manual arehereby incorporated by reference into the present application to thesame extent as if fully set forth herein. This manual is available uponrequest by writing to Adaptec, Inc. at the above address.

It is to be expressly understood that the claimed invention is not to belimited to the description of the preferred embodiment but encompassesother modifications and alterations within the scope and spirit of theinventive concept.

We claim:
 1. A method of testing a chip having embedded circuitry devoidof a direct connection external to said chip; said method comprising thesteps of:programming a tracing means embedded on said chip to detect thepresence of specified information on a bus system embedded on said chip,wherein said bus system is devoid of a direct connection external tosaid chip; operating an address comparator in said tracing means todetect the presence of said specified information on said bus system;opening a gating means in said tracing means in response to saiddetection; extending said specified information on said bus systemthrough said gating means to a buffer memory; writing said specifiedinformation into said buffer memory in response to said extension;reading out said specified information from said buffer memory; andextending said readout information to a user terminal external to saidchip.
 2. A method of testing a chip having embedded circuitry devoid ofa direct connection external to said chip;wherein said embeddedcircuitry includes a processor for controlling the operation of saidcircuitry on said chip and further includes a bus system connecting saidprocessor to a tracing means; said bus system comprising a data bus andan address bus; said method comprising the steps of:programming saidtracing means embedded on said chip to detect the presence of specifiedinformation on said bus system, wherein said bus system is devoid of adirect connection external to said chip; sending a tracing command tosaid processor specifying that a specified address on said bus system isto be traced; sending said specified address from said processor to saidtracing means; storing said specified address in an address register insaid tracing means for detecting a subsequent appearance of saidspecified address on said bus system; operating an address comparator insaid tracing means to detect the presence of said specified informationon said bus system; opening a gating means in said tracing means inresponse to said detection; extending said specified information on saidbus system through said gating means to a buffer memory; writing saidspecified information into said buffer memory in response to saidextension; reading out said specified information from said buffermemory; and extending said readout information to a user terminalexternal to said chip.
 3. A method of testing a chip having embeddedcircuitry devoid of a direct connection external to said chip; saidmethod comprising the steps of:programming a tracing means embedded onsaid chip to detect the presence of specified information on a bussystem embedded on said chip, wherein said bus system is devoid of adirect connection external to said chip; operating an address comparatorin said tracing means to detect the presence of said specifiedinformation on said bus system; opening a gating means in said tracingmeans in response to said detection; extending said specifiedinformation on said bus system through said gating means to a buffermemory; operating said buffer memory external to said chip; writing saidspecified information into said buffer memory in response to saidextension; reading out said specified information from said buffermemory; and extending said readout information to a user terminalexternal to said chip.
 4. A method of testing a chip having embeddedcircuitry devoid of a direct connection external to said chip; saidmethod comprising the steps of:programming a tracing means embedded onsaid chip to detect the presence of specified information on a bussystem embedded on said chip, wherein said bus system is devoid of adirect connection external to said chip; operating an address comparatorin said tracing means to detect the presence of said specifiedinformation on said bus system; opening a gating means in said tracingmeans in response to said detection; extending said specifiedinformation on said bus system through said gating means to a buffermemory; operating said buffer memory embedded on said chip; writing saidspecified information into said buffer memory in response to saidextension; reading out said specified information from said buffermemory; and extending said readout information to a user terminalexternal to said chip.
 5. The method of claim 2 wherein a plurality ofmultiplexor gates are connected to said buffer memory; and wherein saidstep of extending comprises the steps of:opening an multiplexor gateindividual to said tracing means; and extending said specifiedinformation from said tracing means through said multiplexor gate tosaid buffer memory.
 6. The method of claim 5 wherein said step ofreading out includes the steps of:opening an multiplexor gate unique tosaid processor; extending said readout information through said lastnamed multiplexor gate to said processor; and extending said readoutinformation from said processor to said user terminal external to saidchip.
 7. The method of claim 2 wherein said step of programming saidtracing means comprises the steps of:storing user programs in a firstportion of a ROM; storing tracing programs in a second potion of saidROM; operating said processor under control of said user programs whensaid processor is not executing a tracing operation; and operating saidprocessor under control of said tracing programs in said ROM when saidprocessor is executing a tracing operation.
 8. The method of claim 7further including the steps of:activating a tracing program in said ROMin response to the reception of said tracing command by said processor;executing said tracing program in said ROM under control of saidprocessor to program said tracing means.
 9. A method of testing a chiphaving embedded circuitry devoid of a direct connection external to saidchip; said method comprising the steps of:programming a tracing meansembedded on said chip to detect the presence of specified information ona bus system embedded on said chip, wherein said bus system is devoid ofa direct connection external to said chip; operating an addresscomparator in said tracing means to detect the presence of saidspecified information on said bus system; opening a gating means in saidtracing means in response to said detection; extending said specifiedinformation on said bus system through said gating means to a buffermemory, said buffer memory has a first segment for serving host requestand a second segment for serving tracing functions; writing saidspecified information into said buffer memory in response to saidextension; reading out said specified information from said buffermemory; and extending said readout information to a user terminalexternal to said chip.
 10. An apparatus for testing a chip havingembedded circuitry devoid of a direct connection external to saidchip;said apparatus comprising:programming tracing means embedded onsaid chip to detect the presence of specified information on a bussystem embedded on said chip and devoid of a direct connection externalto said chip; an address comparator in said tracing means for detectingthe presence of said specified information on said bus system; means foropening gating means in said tracing means in response to saiddetection; means for extending said specified information on said bussystem through said gating means to a buffer memory; means for writingsaid specified information into said buffer memory in response to saidextension means for reading out said specified information from saidbuffer memory; and means for extending said readout information to auser terminal external to said chip.
 11. An apparatus for testing a chiphaving embedded circuitry devoid of a direct connection external to saidchip;wherein said embedded circuitry includes a processor forcontrolling the operation of said circuitry on said chip and furtherincludes a bus system connecting said processor to a tracing means; saidbus system comprising a data bus and an address bus; said apparatuscomprising:programming tracing means embedded on said chip to detect thepresence of specified information on said bus system embedded on saidchip and devoid of a direct connection external to said chip; means forsending a command to said processor specifying that a specified addresson said bus system is to be traced; means for sending said specifiedaddress to said tracing means; means for storing said specified addressin an address register in said tracing means for detecting a subsequentappearance of said specified address on said bus system; an addresscomparator in said tracing means for detecting the presence of saidspecified information on said bus system; means for opening gating meansin said tracing means in response to said detection; means for extendingsaid specified information on said bus system through said gating meansto a buffer memory; means for writing said specified information intosaid buffer memory in response to said extension; means for reading outsaid specified information from said buffer memory; and means forextending said readout information to a user terminal external to saidchip.
 12. The apparatus of claim 11 wherein said buffer memory isexternal to said chip.
 13. The apparatus of claim 11 wherein said buffermemory is embedded on said chip.
 14. The apparatus of claim 11 wherein aplurality of multiplexor gates are connected to said buffer memory; andwherein said means for extending comprises:means for opening anmultiplexor gate individual to said tracing means; and means forextending said specified information from said tracing means to saidbuffer memory.
 15. The apparatus of claim 14 wherein said means forreading out includes:means for opening an multiplexor gate unique tosaid processor; means for extending said readout information throughsaid last named multiplexor gate to said processor; and means forextending said readout information from said processor to said userterminal external to said chip.
 16. The apparatus of claim 11 whereinsaid means for programming said tracing means comprises:means forstoring user programs in a first portion of a ROM; means for storingtracing programs in a second potion of said ROM; means for operatingsaid processor under control of said user programs when said processoris not executing a tracing operation; means for operating said processorunder control of said tracing programs in said ROM when said processoris executing a tracing operation.
 17. The apparatus of claim 16 furtherincluding:means for activating a tracing program in said ROM in responseto the reception of said tracing command by said processor; means forexecuting said tracing program under control of said processor toprogram said tracing means.
 18. An apparatus for testing a chip havingembedded circuitry devoid of a direct connection external to said chip;said apparatus comprising:programming tracing means embedded on saidchip to detect the presence of specified information on a bus systemembedded on said chip and devoid of a direct connection external to saidchip; an address comparator in said tracing means for detecting thepresence of said specified information on said bus system; means foropening gating means in said tracing means in response to saiddetection; means for extending said specified information on said bussystem through said gating means to a buffer memory, said buffer memoryhas a first segment for serving host request and a second segment forserving tracing functions; means for writing said specified informationinto said buffer memory in response to said extension; means for readingout said specified information from said buffer memory; and means forextending said readout information to a user terminal external to saidchip.
 19. Apparatus for testing a chip having embedded circuitry that isdevoid of direct connections external to said chip; said embeddedcircuitry comprising:a processor for controlling the operation of saidcircuitry; tracing means separate from said processor; a memory a bussystem interconnecting said processor and said tracing means; means forprogramming said tracing means to detect the presence of specifiedinformation on said bus system; means including said tracing means fordetecting the presence of said specified information on said bus system;means including said tracing means for writing said specifiedinformation on said bus system into said buffer memory in response tosaid detection; and means for reading out said specified informationfrom said buffer memory; and means for applying said readout informationto a user terminal.
 20. An apparatus for testing a chip having embeddedcircuitry devoid of a direct connection external to said chip; saidapparatus comprising:an interface for receiving read/write requests froma host; programming tracing means embedded on said chip to detect thepresence of specified information on a bus system embedded on said chipand devoid of a direct connection external to said chip; an addresscomparator in said tracing means for detecting the presence of saidspecified information on said bus system; means for opening gating meansin said tracing means in response to said detection; means for extendingsaid specified information on said bus system through said gating meansto a buffer memory; a multiplexor connected to said buffer memory; adisk drive; means responsive to the reception by said interface of arequest from said host for controlling said multiplexor to connect saidhost with said buffer memory through said multiplexor; means for writinginformation pertaining to said host request into said buffer memory viasaid multiplexor; means for writing said specified information into saidbuffer memory in response to said extension; means including saidmultiplexor responsive to said writing for disconnecting said interfacefrom said buffer memory and for connecting a disk drive through saidmultiplexor with said buffer memory; means for transmitting saidinformation in said buffer memory pertaining to said host request fromsaid buffer memory to said disk drive; means for connecting said tracingmeans via said multiplexor to said buffer in response to the presence ofsaid specified information on said bus system; said tracing means beingeffective when connected to said buffer memory for writing saidspecified information into said buffer memory; means for reading outsaid specified information form said buffer memory; and means forextending said readout information to a user terminal external to saidchip.
 21. An apparatus for testing a chip having embedded circuitrydevoid of a direct connection external to said chip; said apparatuscomprising:programming tracing means embedded on said chip to detect thepresence of specified information on a bus system embedded on said chipand devoid of a direct connection external to said chip; an addresscomparator in said tracing means for detecting the presence of specifiedinformation on said bus system, wherein said address comparator definesmeans for detecting a specified address on said bus system; means foropening gating means in said tracing means in response to saiddetection; means for extending said specified information on said bussystem through said gating means to a buffer memory; means for writingsaid specified information into said buffer memory in response to saidextension; means for reading out said specified information from saidbuffer memory; and means for extending said readout information to auser terminal external to said chip.
 22. An apparatus for testing a chiphaving embedded circuitry devoid of a direct connection external to saidchip; said apparatus comprising:programming tracing means embedded onsaid chip to detect the presence of specified information on a bussystem embedded on said chip and devoid of a direct connection externalto said chip; an address comparator in said tracing means for detectingthe presence of specified information on said bus system, wherein saidaddress comparator defines means for detecting a plurality of specifiedaddresses on said bus system; means for opening gating means in saidtracing means in response to said detection; means for extending saidspecified information on said bus system through said gating means to abuffer memory; means for writing said specified information into saidbuffer memory in response to said extension; means for reading out saidspecified information from said buffer memory; and means for extendingsaid readout information to a user terminal external to said chip. 23.An apparatus for testing a chip having embedded circuitry devoid of adirect connection external to said chip; said apparatuscomprising:programming tracing means embedded on said chip to detect thepresence of specified information on a bus system embedded on said chipand devoid of a direct connection external to said chip; an addresscomparator in said tracing means for detecting the presence of specifiedinformation on said bus system, wherein said address comparator definesmeans for detecting a range of specified addresses on said bus system;means for opening gating means in said tracing means in response to saiddetection; means for extending said specified information on said bussystem through said gating means to a buffer memory; means for writingsaid specified information into said buffer memory in response to saidextension; means for reading out said specified information from saidbuffer memory; and means for extending said readout information to auser terminal external to said chip.